The invention relates to an array substrate and manufacturing method thereof, and a display device.
The array substrate is an important component of the display device, and the array substrate mainly includes a substrate body, a gate electrode layer, a first insulating layer, an active layer, a source-drain electrode layer, a second insulating layer and a transparent conducting layer. Wherein, the pattern in the gate electrode layer may include a gate electrode and a gate electrode line, the pattern in the source-drain electrode layer may include a source electrode, a drain electrode and a data line, and the pattern in the transparent conducting layer may include a pixel electrode.
It is required to electrically connect the pattern in the gate electrode layer with the pattern in the source-drain electrode layer on a plurality of areas of the array substrate, for example electrically connecting the gate electrodes with the source electrodes (or the drain electrodes) of different TFTs (Thin Film Transistor) in a GOA (Gate Driver on Array) unit, electrically connecting a drain electrode with a gate line of a TFT in a GOA unit, and electrically connecting the gate electrodes with the source electrodes (or the drain electrodes) of different TFTs in an electrostatic discharge circuit, and so on. As shown in FIG. 1A, the array substrate includes a substrate body 1 and first insulating layer 3. As shown in FIG. 1A and FIG. 1B, a structure for electrically connecting the pattern in the gate electrode layer with the pattern in the source-drain electrode layer is that the gate electrode layer further includes a gate connecting part 2 which is connected with the pattern to be electrically connected in the gate electrode layer; the source-drain electrode layer further includes a source-drain connecting part 4 which is connected with the pattern to be electrically connected in the source-drain electrode layer; the transparent conducting layer further includes a bridging part 6, wherein one end of the bridging part 6 is connected with the gate connecting part 2 by a via hole, and the other end is connected with the source-drain connecting part 4 by a via hole.
However, the static charges may be easily generated in the procedure of deposition of the second insulating layer 5, and the static charges will accumulate on the source-drain connecting part 4 under the second insulating layer 5 such that a potential difference will occur between the gate connecting part 2 and the source-drain connecting part 4. Since the resistance of the bridging part 6 for electrically connecting the gate connecting part 2 with the source-drain connecting part 4 is relatively low, the flow of the static charges is relatively fast, leading to a ESD (Electro Static Discharge) phenomenon produced between adjacent ends of the gate connecting part 2 and the source-drain connecting part 4 as shown by the dotted circle in FIG. 1.